1. Technical Field
The present invention relates to a printed wiring board having a small difference in thickness between the conductor layers formed on the front and back surfaces and a producing method thereof.
2. Background
When a circuit is formed on a board, there are a subtractive method and an additive method. The subtractive method includes a limit to forming a fine pattern because the accuracy of the circuit width is determined by the conductor thickness as described in JP 2010-87213 A.
In contrast to this, the additive method is excellent in the high-precision fine pattern formation of, for example, ±10 μm in the circuit width of 50 μm or less because the accuracy of the circuit width is hardly affected by the conductor thickness. The additive method includes a full-additive method and a semi-additive method, and the mainstream technology is the semi-additive method. Furthermore, the semi-additive method includes a MSAP (Modified Semi Additive Process) as the derived technology.
In the semi-additive method, a seed layer of electroless plating is formed on the entire insulating resin, and a plating resist is formed on the seed layer as described in JP 2003-8222 A and JP 2007-88476 A. Then, the plating resist is exposed and developed, and the plating resist in a place where a circuit pattern, a via hole and the like are desired to be formed is removed. Then, a circuit pattern, a via hole, and the like are formed by electrolytic pattern plating in the portion where the plating resist is removed. Lastly, the plating resist is removed, the seed layer (electroless plating layer) is removed by flash etching, and the electroless plating catalyst is removed, whereby a circuit is formed.
MSAP uses the copper laminated on the insulating resin layer as a seed layer as described in JP 2007-88476 A, and is the same as the semi-additive method except that the catalyst removal is not required. In MSAP, when a via hole is formed, the electroless plating is required as a seed layer at least on the inner wall of a hole formed as a via hole, however, the electroless plating on the entire insulating resin surface is not required as in the semi-additive method. Therefore, the seed layer can be formed relatively easily. Furthermore, there is no need to remove the palladium used as the catalyst during the electroless plating. Based on these characteristics, the MSAP can form a fine circuit relatively more easily than the semi-additive method.
In the subtractive method described in JP 2010-87213 A, the lower part of the circuit becomes skirt shape trailing long on both sides. The trailing amount is determined by the thickness of the conductor layer, and the thinner the circuit is, the higher the ratio of the trailing amount to the circuit width is. Therefore, when a fine circuit is attempted to be formed, the cross-sectional shape of the conductor layer forming the circuit becomes close to a trapezoid. The cross-sectional shape becomes a triangle in a further thinner circuit, and in an extreme example, the trailing becomes too large to configure the vertices of a triangle, the conductor thickness and the circuit width become smaller than the design value, whereby the circuit formation cannot be said as normal any longer. In a circuit having such a shape, there is also a problem that the electrical characteristics are not stable.
In the electrolytic pattern plating performed in the semi-additive method and the MSAP described in JP 2003-8222 A and JP 2007-88476 A, the problems such as the following (I) and (II) can be mentioned:
(I) The thickness of the conductor layer (plating thickness) is greatly affected by the density of the pattern.
The current density for performing the electrolytic pattern plating is affected by the density of the circuit pattern area, and therefore, when the surface includes a region having a dense pattern area and a region having a sparse pattern area, the distribution of the plating thickness becomes poorer. Therefore, it is difficult to make a surface having a uniform plating thickness. In particular, when the circuit pattern area on each of the front and back surfaces of the insulating board is not the same, the densities of the circuit patterns are largely different, and the like, the current density increases on the surface of the sparse pattern, and the conductor layer (plating thickness) becomes thicker. On the contrary, there are problems that the current density decreases on the surface of the dense pattern, and the conductor layer (plating thickness) becomes thinner.
(II) The reduction of the plating thickness by a sneak current value.
During the electrolytic pattern plating, when the areas of the circuit patterns are largely different on the front and back surfaces of the board, and different current values are passed on the front and back surfaces, the sneak current value phenomenon occurs on the surface of the lower current value. Therefore, when the boards are continuously input, the tendency that the plating thickness is reduced in accordance with the plating input order can be confirmed. It is necessary to input more boards than the number of normal dummy boards for the mitigation of the phenomenon, however, this does not solve the problem completely.
When different current values are passed on the front and back surfaces, the amount of sneak current value is different depending on the number of input boards. From the influence, the phenomenon that the plating thickness of each panel changes depending on the number of boards to be input occurs.